0.7 V Manchester carry look-ahead circuit using PD SOI CMOS asymmetrical dynamic threshold pass transistor techniques suitable for low-voltage CMOS VLSI systems

Dept. of Electr. Eng., National Taiwan Univ.T. Y. ChiangJAMES-B KUO2018-09-102018-09-102005-04https://www.scopus.com/inward/record.uri?eid=2-s2.0-20444448936&doi=10.1049%2fip-cds%3a20041138&partnerID=40&md5=ff0b71243a1b9dd8c999e9fbaf45c7a5The authors report a 0.7 V Manchester carry look-ahead circuit using partially depleted (PD) SOI CMOS dynamic threshold (DTMOS) techniques for low-voltage CMOS VLSI systems. Using an asymmetrical dynamic threshold pass-transistor technique with the PD-SOI DTMOS dynamic logic circuit, this 0.7 V PD-SOI DTMOS Manchester carry look-ahead circuit has an improvement of 30% in propagation delay time compared to the conventional Manchester carry look-ahead circuit based on two-dimensional device simulation MEDICI results. © IEE, 2005.application/pdf880071 bytesapplication/pdfCMOS integrated circuits; Electric network analysis; Leakage currents; Logic circuits; Silicon on insulator technology; Threshold voltage; Transistors; Arithmetic circuits; Asymmetrical dynamic threshold pass-transistors (ADTPT); Dynamic threshold pass-transistors (DTPT); Partially depleted (PD) SOI CMOS; VLSI circuits0.7 V Manchester carry look-ahead circuit using PD SOI CMOS asymmetrical dynamic threshold pass transistor techniques suitable for low-voltage CMOS VLSI systemsjournal article10.1049/ip-cds:200411382-s2.0-20444448936