林浩雄臺灣大學：電機工程學研究所朱文定Chu, Wen-TingWen-TingChu2007-11-262018-07-062007-11-262018-07-062005http://ntur.lib.ntu.edu.tw//handle/246246/53357本研究主題為分離式閘極非揮發性記憶體製程改進及電性分析研究。記憶體中使用一種類似LOCOS的製程可用來產生一個多晶矽尖角，以增強電場，並藉由Fowler-Nordheim (F-N) tunneling作記憶胞(memory cell)抹除(erase)。我們發現穿隧氧化層(tunnel oxide) 電荷捕捉效應，在不同的抹除電壓下，當記憶胞讀取是操作在線性區時，較高的抹除電壓會導致較快的記憶胞電流下跌，也就是說更多的電荷被捕捉到。對浮極(floating gate)接出的元件作F-N tunneling測試時，當跨在氧化層的電場愈高，則愈多的電子被捕捉到。經過250O C烘烤之後，在愈高電壓下氧化層所捕捉到的電荷愈難被釋放出來。 針對full-featured EEPROM，我們提出一種高源極偶合比(coupling ratio)的設計用在分離式閘極記憶胞，其記憶胞面積小於22F2 。一般傳統的記憶胞須要一個選擇電晶體，所以面積無法很小。利用禁止(inhibited)源極電壓加在沒選到的記憶胞，就可達到bit-抹除的功能。此記憶胞擁有很好的抗程式(program)和抹除干擾(disturb)的能力。且可通過300k次程式/抹除耐受度(endurance)測試；而且經過耐受度測試後，此記憶胞會有更好的抗抹除干擾的能力。 此外，我們首先提出一種p型的分離式閘極快閃(flash)記憶胞加入一個多晶矽尖角的結構可降低抹除電壓到12V。我們也評估通道熱電洞撞擊產生熱電子(channel-hot-hole impact ionization induced channel-hot-electrons (CHE))和能隙到能隙穿隧產生的熱電子(band-to-band tunneling induced hot electrons (BBHE))等兩種程式的方法。BBHE 的方法比起用CHE 在注入效率上，大約多了兩個數量級。此記憶胞亦擁有很好的抗程式干擾的能力，而程式干擾是一個主要的問題，在p型的堆疊式閘極記憶胞，此兩種程式方法皆可達到300k次的耐受度測試。 在多晶矽氧化時，鳥嘴(bird’s beak)會伸到氮化矽層下，特別是沿著多晶矽的grain boundary，如此會造成浮極的間距大小不一，甚至會連在一起，如此則記憶胞的面積便無法再縮小。我們提出使用氨氣來氮化多晶矽的表面，可避免鳥嘴連在一起和浮極的間距不均勻；浮極的間距可因此從0.09 mm改善到0.03 mm。由XPS 的分析可發現經過氨氣氮化的多晶矽表面的氧化氮化矽層的厚度小於5 nm。 我們也首先利用0.13 mm 銅製程開發出三重自我對準的分離式閘極快閃記憶胞，自我對準的結構主要是後層對前層的垂直壁做一個spacer。 當記憶胞面積縮小時，由於較大的縱深比，spacer會更容易形成，且形狀更好，長度更易控制。另外此方法所用的製程皆和標準的邏輯製程相容。其字元線的通道長度為0.11 mm，記憶胞的面積小於13F2和堆疊式閘極記憶胞相當。電性分析顯示其程式和抹除的速度皆相當不錯，且可通過300k次的耐受度測試，並有相當好的抗程式干擾的表現。The study presented in this thesis is dedicated to split-gate non-volatile memory process technology improvement and cell characterization. A sharp poly-tip structure, generated by using a LOCOS-like approach is introduced to increase the electric field when the cell is erased using Fowler-Nordheim (F-N) tunneling through poly-poly oxide. The tunnel oxide charge trapping effect under various erase voltages is studied. When reading the cell in the linear region, it was found that the higher the erase voltage applied, the faster the cell current degraded, the greater the likelihood of charges being trapped in the oxide. By observing the F-N tunneling stress on floating gate (FG) connected devices, we also found that the higher the electric field across the oxide, the more the electrons are trapped. After 250O C baking, the oxide trapped charges created by the higher stress voltage are more difficult to heal than those created by a lower stress voltage. A high source-coupling ratio design for full-featured EEPROM composed of one-transistor split-gate cells with a cell area of less than 22F2 is first proposed in this study. This is in contrast to a traditional cell that requires an extra select-transistor and is not effective for cell size when compared to the new design cell. In this design, an inhibited source voltage is used for the unselected cell to achieve bit erase. It has demonstrated excellent program and erase disturb margins and has passed a 300k program/erase (P/E) cycling test. It was found that after the P/E cycling stress, the cell gains a better erase disturb immunity. A p-channel split-gate flash memory cell, employing a field-enhanced structure, is also demonstrated in this study. The erase voltage is as low as 12 V. In cell programming, both channel-hot-hole impact ionization induced channel-hot-electrons (CHE) and band-to-band tunneling induced hot electrons (BBHE) are evaluated. BBHE shows an injection efficiency of ~2 orders in magnitude higher than that of CHE. The cell also demonstrated an acceptable program disturb window, which is of high concern in a p-channel stacked-gate cell. Both programming approaches can pass 300k P/E cycles. During poly oxidation, the bird’s beak encroaches under the SiN film, especially along the poly grain boundary, causing non-uniform FG spacing, even bridging, which is an obstacle to cell shrinkage. We proposed an ammonia treatment on the poly to nitridize the poly surface, thereby avoiding bird’s beak bridging. After the ammonia treatment, FG spacing is quite uniform and can be improved from 0.09 mm to 0.03 mm. The XPS analysis on the ammonia treated poly shows the oxynitride thickness is less than 5 nm. A shrinkable triple self-aligned split-gate flash cell fabricated using a 0.13-mm copper interconnect process is firstly demonstrated in this study. The approach used here to create a self-aligned structure is to form a spacer against the prior layer. Due to a higher aspect ratio when the cell pitch decreases, the profile of the spacer structure becomes sharper. This improves process control of the spacer profile and length. All processes used here are compatible with standard logic process. The word line channel length of the cell is 0.11 mm. The cell area is comparable to that of a stacked-gate cell and can be less than 13F2. Characterization shows considerable program and erase speed, up to 300k P/E cycles, and excellent disturb margins.摘要. I Abstract. III Figure Captions. VII Chapter 1 Introduction. 1 1.1 Non-Volatile Memory Introduction. 1 1.2 An Outline of the Dissertation 2 Chapter 2 The Process and Electrical Characterization of a Split-Gate Cell. 6 2.1 Effect of Erase Voltage on Tunnel Oxide Trapping and Endurance Performance. 6 2.2 Erase Voltage Optimization. 11 Chapter 3 Full-Featured EEPROM Using High Source-Coupling Ratio Design. 20 3.1 Brief Introduction. 20 3.2 Device Fabrication. 21 3.3 Results and Discussion. 21 3.4 Summary. 23 Chapter 4 P-channel Split-Gate Cell with a Field-Enhanced Structure. 33 4.1 Brief Introduction. 33 4.2 Device Fabrication. 34 4.3 Cell Characterization. 34 4.4 Summary. 36 Chapter 5 Using an Ammonia Treatment to Improve the Floating-Gate Spacing. 46 5.1 Brief Introduction. 46 5.2 Experiment. 46 5.3 Results and Discussion. 47 5.4 Summary. 48 Chapter 6 Shrinkable Triple Self-Aligned Field-Enhanced Split-Gate Flash Memory. 55 6.1 Brief Introduction. 55 6.2 Device Fabrication. 55 6.3 Cell Characterization. 57 6.4 Summary. 59 Chapter 7 Summary. 72 7.1 Conclusion. 72 7.2 Prospective Plans. 74 References. 761090424 bytesapplication/pdfen-US分離式閘極自我對準多晶矽尖角非揮發性記憶體快閃記憶體field-enhanced structuredisturbflashsplit-gatesource-couplingfull-feature EEPROMp-channelself-alignedthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53357/1/ntu-94-D89921006-1.pdf