Wu, Ching YangChing YangWuTsai, Chieh JuChieh JuTsaiCHING-JAN CHENTu, Chien ChengChien ChengTuWang, Szu TingSzu TingWangWen, Yong HwaYong HwaWen2023-08-212023-08-212023-01-019798350334166https://scholars.lib.ntu.edu.tw/handle/123456789/634628This paper presents a 200 nA quiescent current, 4.8 MHz Fsw, all N-FINFET power stage buck converter with passive ramp (PSR) on-off-time control for a modern mobile silicon-on-chip (SoC). During DCM, only the main comparator is alive to maximize the light-load efficiency. An N-FinFET power stage with co-package designed debounce circuitry and bootstrap circuit performs a 35 mOhm Rdson with all trace resistance. As a result, the efficiency > 90% range is from 1 μ A to 2 A. The proposed passive ramp constant-on-off time controller achieves a 23 mV/17 mV undershoot/overshoot voltage with 800 ns settling time with a 1 μ A to 500 mA loading step.buck converter | FinFET | low Iq | N-FinFET power stage | on-off-time control | passive ramp[SDGs]SDG7conference paper10.1109/VLSI-TSA/VLSI-DAT57221.2023.101339902-s2.0-85163028931https://api.elsevier.com/content/abstract/scopus_id/85163028931