A New Method for Two-Dimensional VLSI Layout Compaction Design

Chen, H. F.H. F.ChenHsiao, P, Y.P, Y.Hsiao馮武雄陳少傑Feng, Wu-ShiungWu-ShiungFengChen, Sao-JieSao-JieChen2009-02-042018-07-062009-02-042018-07-061990-03http://ntur.lib.ntu.edu.tw//handle/246246/121113Hsitouen-USA New Method for Two-Dimensional VLSI Layout Compaction Designconference paper