Hong, C.-C.C.-C.HongJENN-GWO HWU2018-09-102018-09-102001https://www.scopus.com/inward/record.uri?eid=2-s2.0-0035803250&doi=10.1063%2f1.1420491&partnerID=40&md5=33ad257037e3a20d540b20bf6b7e1c0cThe effect of external stress on metal-oxide-semiconductor (MOS) structure with ultrathin gate oxide (∼1.5 nm) was studied. J - V characteristics of fresh and stressed samples revealed that the tensile stress had little effect on J - V curves, whereas the compressive stress obviously increased the leakage current by about several hundred in percentages with respect to the fresh sample, in both positive and negative gate biases. This increase in leakage current was suggested to be attributed to the increase of interface states and silicon bulk traps under external compressive stress in the MOS device with an inherent tensile stressed silicon. In addition, we also found that once the device was damaged by the previously applied compressive stress, the second applied compressive stress of the same magnitude would not create more damage unless the device was breakdown. © 2001 American Institute of Physics.journal article10.1063/1.14204912-s2.0-0035803250