Lu P.-YYen C.-MChang S.-YFeng Y.-JLien CHu C.-WYao C.-WLee M.-HLiao M.-H.MING-HAN LIAO2021-08-052021-08-0520200163-1918https://www.scopus.com/inward/record.uri?eid=2-s2.0-85102939120&doi=10.1109%2fIEDM13553.2020.9371949&partnerID=40&md5=0f801b38e978a8e3a93c46c69b859b56https://scholars.lib.ntu.edu.tw/handle/123456789/576187With the excellent material properties of Carbon Nano-tubes (CNTs) developed in this work (Coefficient of Thermal Expansion~-2 x 10-6 K-1, Resistivity~10-6 Ω-m, Young's modulus~1000 GPa, and thermal conductivity ~800 Wm-1K-1), the real 3D integrated circuits (ICs) system with CNTs as the high aspect ratio (>25)/small diameters (<5 μm) Through Silicon Vias (TSVs) is demonstrated. The device temperature can be reduced ~15 °C and the keep-out zone region can be reduced ~80%. on the other hand, the CNTs 3DICs system also shows that the better system-level electrical performance from the latency, bandwidth density, power density, and reliability (~10X) points of view. The developed technologies including (1) High quality CNTs growing at the low temperature (550 °C) using a novel gas Fe(C5H5)2 reactant, (2) Optimized wafer bonding process, (3) Non-mask laser engrave patterning, and (4) wafer transfer technology by a thermal release tape/ethylene viny acetate processes provide the useful solution for the applications of CNTs as a vertical connection material in the near coming high-density 3D device. ? 2020 IEEE.Aspect ratio; Carbon nanotubes; Elastic moduli; Electron devices; Electronics packaging; Integrated circuit interconnects; Iron compounds; Laser materials processing; Silicon wafers; Temperature; Thermal conductivity; Thermal expansion; Wafer bonding; 3d integrated circuit (ICs); Carbon nano tube (CNTs); Device temperature; Electrical performance; High aspect ratio; Through silicon vias; Wafer bonding process; Wafer transfer technologies; Three dimensional integrated circuitsconference paper10.1109/IEDM13553.2020.93719492-s2.0-85102939120