Chan, W.-K.W.-K.ChanTseng, Y.-H.Y.-H.TsengTsung, P.-K.P.-K.TsungChuang, T.-D.T.-D.ChuangTsai, Y.-M.Y.-M.TsaiChen, W.-Y.W.-Y.ChenLIANG-GEE CHENSHAO-YI CHIEN2018-09-102018-09-10201108865930https://www.scopus.com/inward/record.uri?eid=2-s2.0-80455156131&doi=10.1109%2fCICC.2011.6055296&partnerID=40&md5=c2f10ed5c3374adc697a29fac40b6883http://scholars.lib.ntu.edu.tw/handle/123456789/365122A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor is implemented in 90nm CMOS technology. A reconfigurable hardware architecture with heterogeneous stream processing and subword-level parallelism is implemented to accelerate the vision processing for smart-camera applications. The area efficiency reaches 111.329 GOPS/mm2. The power efficiency and area efficiency are 4.5x to 33.0x and 3.8x to 74.2x better than the state-of-the-art works, respectively. © 2011 IEEE.[SDGs]SDG790nm CMOS; Area efficiency; Power efficiency; Re-configurable; Smart-camera; Stream processing; Stream processor; Vision processing; Cameras; CMOS integrated circuits; Computer hardware description languages; Efficiency; Integrated circuit manufacture; Integrated circuits; Reconfigurable hardwareconference paper10.1109/CICC.2011.60552962-s2.0-80455156131