Chang, C.-C.C.-C.ChangSHEN-IUAN LIU2020-06-112020-06-11199500207217https://scholars.lib.ntu.edu.tw/handle/123456789/499827https://www.scopus.com/inward/record.uri?eid=2-s2.0-0029376174&doi=10.1080%2f00207219508926273&partnerID=40&md5=95bca3bf615aaa744f63cb729ac13efaA new CMOS four-quadrant multiplier using active attenuators is presented. Simulation results show that for a power supply of ±5 V, the linear range is over + 1 V with the linearity error less than 0-83%. The total harmonic distortion is less than 1% with an input range up to ± 1 V. The simulated —3dB bandwidth is about 5 MHz. Experimental results show that the linear range is within ± 1 V. The proposed multiplier is expected to be useful in analogue signal processing applications. © 1995 Taylor & Francis Ltd.[SDGs]SDG7Electric attenuators; Error analysis; Integrated circuit layout; Mathematical models; Multiplying circuits; Numerical analysis; Signal distortion; Active attenuators; Analogue signal processing; Four quadrant multiplier; Harmonic distortion; Linearity error; CMOS integrated circuitsjournal article10.1080/002072195089262732-s2.0-0029376174