VLSI architecture for radix-2k Viterbi decoding with transpose algorithm

Dept. of Electr. Eng., National Taiwan Univ.Lee, Wen-TaWen-TaLeeChen, Thou-HoThou-HoChenLIANG-GEE CHEN2007-04-192018-07-062007-04-192018-07-061995-06http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032063https://www.scopus.com/inward/record.uri?eid=2-s2.0-0029509877&partnerID=40&md5=5a062c3e75338ef1101489467bcd1329The paper presents a novel transpose path metric (TPM) algorithm to reduce the interconnection routing complexity for radix-2k Viterbi decoder. With simple local interconnections, the algorithm can provide a permutation function for state rearrangement in a transpose strategy. With features of modulation and regularity, this algorithm is very suitable for VLSI implementation; consequently, a larger memory length VA decoder can be constructed with several smaller memory length modules. Finally, a VLSI architecture for 16-states radix-4 VA decoder using TPM has been developed.application/pdf488368 bytesapplication/pdfen-USAlgorithms; Computation theory; Computational complexity; Computer architecture; Convolutional codes; Data storage equipment; Decoding; Modulation; Shift registers; VLSI circuits; Decoder; Interconnection routing complexity; Permutation function; Radix; Transpose path metric; Viterbi decoder; Data communication equipmentVLSI architecture for radix-2k Viterbi decoding with transpose algorithmconference paper10.1109/VTSA.1995.5246672-s2.0-0029509877http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032063/1/00524667.pdf