國立臺灣大學電機工程學系暨研究所賴飛羆2006-07-252018-07-062006-07-252018-07-062003-07-31http://ntur.lib.ntu.edu.tw//handle/246246/7913隨著奈米製程的的開發,單位面積所 必須容納的邏輯閘數大幅增加,在要求效 能的情形下,晶片工作頻率亦不斷向上攀 升。然而面臨到的問題卻是在單位面積所 呈現的功率消耗極度龐大,因而造成了散 熱與系統穩定性等問題。若晶片使用於需 電池供應電源的設備上,則更直接關係到 操作時間的長短。大多數在電路上的低功 率研究都著眼於邏輯區塊的最佳化。然 而,由於傳輸資料大量運作在晶片內部的 匯流排上,使得匯流排的功率消耗在整體 晶片的功率比率上一直居高不下。在匯流 排的問題中,由於鄰近的兩條傳輸線會有 互相干擾的情形,使得傳輸的資料發生錯 誤,造成訊號必須重新傳輸,使功率消耗 及時間延遲上都增加了額外的負擔。因 此,本計畫便針對此問題,提出了一個可 以有效解決匯流排上因傳輸線太過靠近而 造成的相互干擾的方法。此方法是基於事 先研究資料傳輸的轉態行為特性,再依照 所得到的訊息,透過一個包含編碼、排列、 與反置的架構來最佳化功率消耗及雜訊干 擾。在所提出來的方法中,我們改進了以 往必須使用大量額外控制電路的缺點,以 較低的延遲及較小的面積負擔來進行控 制。依照研究出的成果,大約可以改進 38.7%的相互干擾。With the development of nanometer, more and more gate counts need to be placed in one chip. Under the performance requirement, the working frequency of a chip also increases continually. The following problems are the power consumption of that chip, the heat problem and the reliability of the chip. It is also related to the operating time of the portable device, while using such chip on a battery operating system. Most low power researches on the circuits focus on optimization the logic blocks. However, there are lots of data need to be transmitted on the on-chip buses, and lead to the power consumption of buses have a high percentage among total power consumption. Among the bus problems, there exists a crosstalk problem while two adjacent wires are too close. It will result in error when data transit, and also increase the loading of power consumption and transition delay. Thus, we proposed a method based on profiling the switching behavior to solve this problem efficiently. This method, based on the profiling information, applying an architecture that encodes pairs of bus wires, permutes the wires and assigns an inversion level to each wire together. Unlike the previous technique, it can reduce the control circuit with small delay and area overhead. As the research results show, it can be improved about 38.7% of the crosstalk problem.application/pdf257598 bytesapplication/pdfzh-TW國立臺灣大學電機工程學系暨研究所低功率匯流排相互干擾基 因演算法low powerbuscrosstalkgenetic algorithm硬體描述語言低功率架構設計(2/3)Low power design in hardware descr iption languagereporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/7913/1/912213E002038.pdf