KUN-YOU LINHuang, J.-Y.J.-Y.HuangHsieh, C.-K.C.-K.HsiehShin, S.-C.S.-C.Shin2018-09-102018-09-102009http://www.scopus.com/inward/record.url?eid=2-s2.0-60449107506&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/349972A broadband balanced distributed frequency doubler fabricated by 0.35 μm SiGe BiCMOS technology is developed to operate from 4 to 18 GHz output frequency. This balanced doubler consists of an active balun and a distributed doubler. A sharing collector line is used in the balanced distributed doubler to reduce the chip size. This circuit exhibits a measured conversion loss of less than 8 dB and a fundamental rejection of better than 23 dB for the output frequency between 4 and 18 GHz. The chip size is 1.1× 0.7 mm 2.Balanced doublerDistributed doublerSiGe BiCMOS[SDGs]SDG7journal article10.1109/LMWC.2008.20113362-s2.0-60449107506