Dept. of Electr. Eng., National Taiwan Univ.Lee, Wen-TaWen-TaLeeChen, Thou-HoThou-HoChenLIANG-GEE CHEN2007-04-192018-07-062007-04-192018-07-061994-12http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032410https://www.scopus.com/inward/record.uri?eid=2-s2.0-0028739717&partnerID=40&md5=fe1800af4fc0d0338690f4bd0248300fIn this paper, we present a radix-2k Viterbi decoding with Transpose Path Metric (TPM) processor. The TPM processor can provide a permutation function for state rearrangement with simple local interconnection. For interconnection realization, the routing complexity is less than that of the delay-commutator reported previously. In addition, a higher memory length Viterbi processor can be constructed with lower radix-2k modules. With features of modulation and cell regularity, the radix-2k Viterbi decoding with TPM processor is very suitable for VLSI implementation.application/pdf566365 bytesapplication/pdfen-USAlgorithms; Computational complexity; Graph theory; Iterative methods; Trellis codes; VLSI circuits; Add compare select; Transpose path metric processor; Trellis diagram; Viterbi decoding; Decodingconference paper10.1109/APCCAS.1994.5145482-s2.0-0028739717http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032410/1/00514548.pdf