郭斯彥臺灣大學：電子工程學研究所黃宏瑋Huang, Hong-WeiHong-WeiHuang2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57616A new high efficiency low noise dynamic voltage scaling (DVS) power management system (PMS) utilizing two regulation stages is described. The former stage of PMS consists of a pulse-width modulation (PWM) control mode and a pulse-frequency modulation (PFM) control mode. According to the output voltage and load current, the control scheme of former stage is switched automatically between both control modes by utilizing a load sensing circuit and looking efficient table up. The latter stage is used to regulate the voltage which is generated from former stage. It consists of two low drop-out (LDO) regulators, one is used with n-channel power device in output range from 0.65v~1.4v and the other is used with p-channel power device in output range from 1.45v~2.2v. By switching the control mode in overall structure of PMS, the maximum efficiency of 87.55% is attained. This chip is fabricated in TSMC 2P4M 0.35μm Mixed Signal process. The switching frequency of PWM and PFM are 500 kHz and 250 kHz, respectively, and the line regulation and load regulations are 4.2% and 0.0735%, respectively. The output voltage ripple is less then 0.15mv in the range of output voltage from 0.65v to 2.2v for load current from 3mA to 400mA and the supply voltage can be endured from 2.5v to 4.5v.Acknowledgement i Abstract ii Contents iii Figure Captions v Table Captions viii Chapter 1 Introduction 1.1 Background and Review 1 1.2 Motivation 2 1.3 Thesis Organization 3 Chapter 2 Fundamentals of DC-DC Converter 2.1 Specifications 4 2.2 Operational Principal of Switching Regulator 6 2.2.1 Buck Converter 8 2.2.2 Boost Converter 12 2.3 PWM Operation 14 2.3.1 Current Programmed Control 16 2.3.2 Design basis 18 2.3.3 Zero-Voltage Switching 19 2.3.4 Sources of dissipation 22 2.4 PFM Operation 23 2.4.1 Design basis 24 2.5 LDO regulator 25 2.5.1 Frequency Response 26 Chapter 3 Circuit Implementation of DVS Power Management System 3.1 System Architecture Design 29 3.2 Soft Start Circuit 31 3.2.1 Operation Principle 33 3.2.2 Sawtooth Circuit 34 3.3 Controller Circuit 36 3.4 PWM Control 37 3.4.1 Compensator 38 3.4.2 Current Sensing Circuit 38 3.4.3 Voltage-to-Current Converter 41 3.4.4 Ramp & Clk Generator 42 3.4.5 Pulse Width Generator 43 3.4.6 Delay Buffer 44 3.5 PFM Control 45 3.6 H-V LDO Regulator 48 3.6.1 Voltage-Controlled Current Source (VCCS) 49 3.7 L-V LDO Regulator 51 3.8 Load Sensing Circuit 51 Chapter 4 Simulated and Experimental Results 4.1 Layout Consideration 57 4.2 Measurement Results 58 Chapter 5 Conclusions and Future Work 5.1 Conclusions 65 5.2 Future Work 66 Reference 68en-US電源管理系統電壓轉換器DC-DC converterpower management systemthesis