Kang W.-CWu J.-YCheng Y.-TWang Y.-FLiao Y.-JTZU-HSUAN CHANG2023-06-092023-06-0920227413106https://www.scopus.com/inward/record.uri?eid=2-s2.0-85129503819&doi=10.1109%2fLED.2022.3157739&partnerID=40&md5=28261500a56faad88bffd54a006980bbhttps://scholars.lib.ntu.edu.tw/handle/123456789/632295Complementary FET (CFET), a transistor architecture to stack pFET-on-nFET or vice versa, is a promising option to reduce the footprint of the logic gates further. The footprint shrinkage over planar logic design inevitably aggregates routing congestion and parasitic RC in the front-end design stages. In this work, we propose the adaptation of double-cell-height design, expanding the transistors of logic gates in two rows instead of only single row connected through top metal layers. Our design effectively reduces the routing congestion and minimizes the increased routing complexity of CFET. Shorter interconnect length and lowered RC delay of NAND cells family are validated through TCAD simulation. Output capacitance is reduced significantly, and the unloaded delay time of the proposed double-cell-height NAND cell can be reduced compared to the traditional single-cell-height design. © 1980-2012 IEEE.CFET; local interconnect; RC delay; transistor-level placementCells; Computer circuits; Cytology; Integrated circuit interconnects; NAND circuits; Cell height; Complementary FET; Double cells; Local interconnects; Parasitics; RC delay; Routing congestion; Transistor architecture; Transistor level; Transistor-level placement; Logic gatesjournal article10.1109/LED.2022.31577392-s2.0-85129503819