張耀文臺灣大學:電子工程學研究所林宜偉Lin, Yi-WeiYi-WeiLin2007-11-272018-07-102007-11-272018-07-102004http://ntur.lib.ntu.edu.tw//handle/246246/57706隨著能量消耗和電路密度的急劇增加,導致晶片操作溫度的升高,影響晶片可靠度以及效能,所以溫度、電子遷移、面積、時序與能量都是奈米時代積體電路設計的重要考量。在本論文中,我們模擬了溫度對連線時序延遲與電子遷移可靠度的影響,並利用最小平方差法,得到 posynomial 方程式去趨近連線溫度,我們依據 Lagrangian relaxation,提出改變電路元件的大小的演算法,此演算法能夠同時處理連線溫度、電子遷移、面積、時序與能量的最佳化。實驗結果顯示,原來 11.56% 不會通過電子遷移可靠度要求的連線,經過我們所提出的演算法能夠找到使得全部連線滿足電子遷移可靠度要求的解,而且平均而言,在面積、最大溫度增加、時序與能量消耗分別有11.84%、10.96%、70.75% 和 12.01% 的進步。The dramatic increase of power consumption and integration density has led to high operating temperature. Temperature, as well as electromigration (EM), area, timing, and power, has become one of the most important concerns in the design of nanometer integrated circuits. In this thesis, we model the effects of thermal on both interconnect delay and EM reliability. Applying the least square estimator (LSE) method, we develop a posynomial formula to approximate interconnect temperature and present an algorithm that can optimally solve the simultaneous interconnect temperature, EM, area, delay, and power optimization problem by sizing circuit components based on Lagrangian relaxation. The experimental results show that our algorithm can find desired solutions that satisfy all EM reliability requirements from 11.56% failures among all wires initially. On the average, it improves the respective area, maximal temperature increase, delay, and power by 11.84%, 10.96%, 70.75%, and 12.01% after wire and gate sizing.Abstract (Chinese) i Abstract ii Acknowledgements iii List of Tables vi List of Figures vii Chapter 1. Introduction 1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 PreviousWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Lagrangian Relaxation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3.1 Basic Lagrangian Relaxation Theory . . . . . . . . . . . . . . . . . 4 1.4 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chapter 2. Preliminaries 11 2.1 The ThermalModel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1 Sources of Power Dissipation . . . . . . . . . . . . . . . . . . . . . 12 2.1.2 Thermal Model and Temperature Calculation . . . . . . . . . . . . 13 2.2 The Thermal Effects on Interconnect . . . . . . . . . . . . . . . . . . . . 16 2.2.1 Current Density Approach . . . . . . . . . . . . . . . . . . . . . . 16 2.2.2 Influence of Self-Heating on EM . . . . . . . . . . . . . . . . . . . 16 2.2.3 Temperature Dependent Delay . . . . . . . . . . . . . . . . . . . . 19 2.3 The RC DelayModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.1 The Lumped RCModel . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.2 The Distributed RCModel . . . . . . . . . . . . . . . . . . . . . . 20 2.3.3 The Elmore RC DelayModel . . . . . . . . . . . . . . . . . . . . . 20 2.4 Circuit Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 Circuit and DelayModels . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.6 ProblemDescription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chapter 3. Thermal-Driven Interconnect Optimization 29 3.1 The Thermal Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2 ProblemFormulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 Lagrangian Relaxation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4 Lagrangian Relaxation Subproblem . . . . . . . . . . . . . . . . . . . . . 38 3.5 Lagrangian Dual Problem . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Chapter 4. Simulations 45 Chapter 5. Conclusions and Future Work 51 5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bibliography 53 v1613206 bytesapplication/pdfen-US連線最佳化熱效應interconnect optimizationthermal effects以熱為導向的連線最佳化THERMAL-DRIVEN INTERCONNECT OPTIMIZATION BY SIMULTANEOUS GATE AND WIRE SIZINGthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57706/1/ntu-93-R91943056-1.pdf