Chang, Yung-ChiYung-ChiChangHuang, Chao-ChihChao-ChihHuangChao, Wei-MinWei-MinChaoLIANG-GEE CHEN2018-09-102018-09-10200513875485https://www.scopus.com/inward/record.uri?eid=2-s2.0-22344452389&doi=10.1007%2fs11265-005-6649-0&partnerID=40&md5=683bda998e2357b80121c1d605279224In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5. © 2005 Springer Science + Business Media, Inc.Bitstream parsing processor; Data partitioned bitstream parsing; MPEG-4; Video decoding[SDGs]SDG7Computer architecture; Computer simulation; Data compression; Data reduction; Optimization; Program processors; Standards; Bitstream parsing processors; Data partitioned bitstream parsing; MPEG-4; Video decoding; Video signal processingAn efficient embedded bitstream parsing processor for MPEG-4 video decoding systemjournal article10.1007/s11265-005-6649-02-s2.0-22344452389