Chien, Chung ChiaChung ChiaChienWang, YunshanYunshanWangNg, Yuen SumYuen SumNgTIAN-WEI HUANGChiong, Chau ChingChau ChingChiongHUEI WANG2023-12-092023-12-092023-01-019782874870736https://scholars.lib.ntu.edu.tw/handle/123456789/637634In this paper, a low power consumption and gm-boosting technique frequency doubler implemented in 28-nm CMOS technology is presented. A 2nd harmonic load-pull approach is utilized, and a maximum output power of 0.5 dBm is achieved at 134 GHz with 7.4% efficiency. The doubler is biased in class-B with 0.4-V Vg for higher Gm2, and it consumes only 12 mW dc power. The doubler covers 126-146 GHz, and achieves 4.5-dB conversion gain with a 3-dB bandwidth of 15%, with 30 dB fundamental rejection. With the Gm-boosting technique, this frequency doubler features high conversion gain.CMOS | D-band | efficiency | frequency doubler | frequency multiplier | millimeter-wave | signal generationconference paper10.23919/EuMIC58042.2023.102887742-s2.0-85177238727https://api.elsevier.com/content/abstract/scopus_id/85177238727