A fast-lock low-power subranging digital delay-locked loop

Chen, H.-S.H.-S.ChenLin, J.-C.J.-C.LinHSIN-SHU CHEN2018-09-102018-09-102010http://www.scopus.com/inward/record.url?eid=2-s2.0-77952968773&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/357877[SDGs]SDG7A fast-lock low-power subranging digital delay-locked loopjournal article10.1587/transele.E93.C.855