貝蘇章臺灣大學：電信工程學研究所陳美代Chen, Mei-DaiMei-DaiChen2007-11-272018-07-052007-11-272018-07-052007http://ntur.lib.ntu.edu.tw//handle/246246/58621本篇論文是以高階數位等化器為基礎，將其原本為串聯的頻率轉換函數以許多不同的架構實現，以便觀察每種結構的差別。雖然套入架構裡面的數學總式是相同的，但是隨著架構設計的不同，會造成不同影響！尤其有是後期所發展出來的架構，因為其參數皆有經過標準化的處理，故其對數字的性質所表現出來的結果會比其他未經標準化的架構穩定很多。 接著將原為串聯的頻率轉換函數導成並聯的形式，並且亦將其用已經討論過的架構實現，去觀察串聯和並聯的差異性。一般來說，並聯的架構對於雜訊的影響會比串聯來的小。 最後則將輸入訊號以及所有的架構的參數以不同的有限長字元長度去做限制與量化，觀察並分析此一舉動所帶來的影響。A family of digital parametric equalizers based on high-order Butterworth, Chebyshev type I, Chebyshev type II, and elliptic analog prototype filter was proposed in [16]. Compared to the conventional biquadratic equalizers, such equalizers can have flatter passband and sharper band edges at the expense of higher computational cost. Here, we will review this kind of equalizer, and realize it by several of structures, such as transposed, ladder and lattice, normalized lattice, state space, and decoupled. The transfer function of this high-order parametric equalizer is first derived in cascade form, and we will derive it in parallel form to observe the effects between the cascade and the parallel form. Then we also set the coefficients of the realization structures to be quantized with the finite word length so that we can observe how the performances are affected by quantization errors.Chapter 1 Introduction.........1 Chapter 2 Review of Method for High-Order Digital Parametric Equalizer Designs........3 2.1 Introduction......3 2.2 General Consideration.....4 2.3 Equalizer Designs in Four Prototype Filters.........12 2.3.1 Designs in Butterworth Prototype Filter..12 2.3.2 Designs in Chebyshev Type I Filter.......14 2.3.3 Designs in Chebyshev Type II Filter......16 2.3.4 Designs in Elliptic Filter...............18 2.4 Experimental Results................................22 2.5 Conclusion..........................................29 Chapter 3 Realization Structures for High-Order Digital Parametric Equalizers in Cascade Form ...30 3.1 Introduction.....30 3.2 Basic Structure in Cascade Form.........31 3.3 Realization Structures..................33 3.3.1 Ladder Realization Structure......33 3.3.2 Ladder and Lattice Realization Structure..37 3.3.3 Transposed Realization Structure..........42 3.3.4 Normalized Lattice Realization Structure..43 3.3.5 State Space Realization Structure.........47 3.3.6 Decoupled Realization Structure...........50 3.4 Experimental Results.....56 3.5 Conclusion...............70 Chapter 4 Realization Structures for High-Order Digital Parametric Equalizers in Parallel Form...........71 4.1 Introduction......71 4.2 Rearrangement of Equalizer Transfer Function in Parallel Form.........72 4.3 Experimental Results.....75 4.4 Conclusion......86 Chapter 5 Analysis of Coefficient Quantization Effects......87 5.1 Introduction......87 5.2 Concept of Coefficient Quantization Errors.........88 5.2.1 Types of Quantization Errors............88 5.2.2 Effects of Coefficient Quantization.....90 5.3 Experimental Results.....92 5.4 Conclusion......100 Chapter 6 Conclusion and Future Work.....101 Reference ........................................102995339 bytesapplication/pdfen-US高階數位等化器串聯頻率轉換函數並聯有限長字元長度量化digital parametric equalizerscascade formparallel formfinite word lengthquantizationthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/58621/1/ntu-96-R94942049-1.pdf