Su, B. -SB. -SSuLee C.-HTZI-DAR CHIUEH2023-06-092023-06-09202225739603https://www.scopus.com/inward/record.uri?eid=2-s2.0-85128322814&doi=10.1109%2fLSSC.2022.3167423&partnerID=40&md5=c279ed650de8b9b2a55001b5cbcc2fd0https://scholars.lib.ntu.edu.tw/handle/123456789/632306This letter presents the first belief propagation (BP) decoder IC implementation for the two forward error correction (FEC) codes in the 5G communication standard. The LDPC mode supports 5G BG2 with 128 lifting size, while the polar mode supports code length N = 1024. The 40-nm CMOS chip features BP module sharing, memory reuse, check node unit design, forwarding and layer pipelining, and dataflow rearrangement. Compared to two single-mode decoders, this dual-mode decoder saved 37% in the overall die area, 32% in the computation circuit area, and 41% in the memory area. The chip delivers throughputs of 2.38 and 1.85 Gb/s from 0.9-V Vdd with energy efficiencies of 58.6 and 91.3 pJ/b in the LDPC mode and the polar mode, respectively. © 2018 IEEE.5G communications; Belief propagation (BP); Forward error correction (FEC) decoder; LDPC code; Polar code[SDGs]SDG75G mobile communication systems; Channel coding; Decoding; Energy efficiency; Forward error correction; Integrated circuits; Satellite communication systems; Signal encoding; Timing circuits; Belief propagation; Belief propagation.; Code; Error correction decoder; Forward error correction decoder; Forward error-correction; Parity check codes; Polar codes; Belief propagationjournal article10.1109/LSSC.2022.31674232-s2.0-85128322814