臺灣大學: 電子工程學研究所張耀文周昇Chou, ShengShengChou2013-04-102018-07-102013-04-102018-07-102012http://ntur.lib.ntu.edu.tw//handle/246246/256710資料路徑是在高性能的電路設計中，用於資料運算最為重要的部分之一。為了對抗現今極速高升的計算複雜度，考慮資料路徑之電路擺置愈來愈為重要。在電路的實體設計中，資料路徑電路規律化及密集化的擺置，有助於提升電路效能。在過去，雖然電路擺置的問題已被廣泛研究，資料路徑電路在電路擺置上的考量卻大多被忽視。在這個論文中，我們提出了一個考慮密集資料路徑結構的擺置演算法。不同於過去的研究，我們以S型(Sigmoid)函數為基礎，提出全新的密度模型，並以非線性最佳化的方式降低線長並獲得高品質的擺置。實驗結果顯示出，我們所提出的方法相較於先前的研究，可以有效地得到最好的電路擺置結果。Datapath is one of the most important components in high performance circuit designs, such as microprocessors, as it is used to manipulate all data. For better performance, a datapath is usually placed with high regularity and compactness. Although cell placement has been studied extensively, not much work addresses the optimization of datapaths, which are often treated as big macros. In this thesis, we propose a structure-aware placement algorithm that can exploit the regular structures of datapath circuits and meanwhile leverage effective techniques to achieve high quality and scalability. Our algorithm applies a nonlinear optimization for wirelength minimization and a sigmoid-based density model for density control during datapath placement. Compared with state-of-the-art works, our algorithm can achieve the best structure-aware placement results efficiently.140 bytestext/htmlen-US實體設計資料路徑電路擺置規律性萃取密度模型physical designdatapathplacementregularity extractiondensity modelthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256710/1/index.html