黃俊郎臺灣大學：電子工程學研究所黎孔平Li, Kong-PingKong-PingLi2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57712在現今的高速通訊元件中，抖動已然成為資料可達到傳送品質的重要因素之一，隨著資料傳送頻寬的需求漸增，抖動的規格對高速傳送系統及匯流排來說是相當重要的。一般而言，元件抖動的規格是由自動測試設備(ATE)所測得的，但是資料頻率的提升使的自動測試設備難以趕上期效能的要求。再者，近來大多數研究投注在抖動量測的部分。在本論文中，我們提出了一個內建抖動注入的方法以測試接受器的抖動容忍度，在目標信號頻率1GHz的條件下，這個方法可以注入達240ps 峰對峰值，且高達8 ps解析度的週期性抖動。For modern high speed communication devices, jitter has been an important factor of the achievable data transmission quality. With the growing demand on data bandwidth, meeting the jitter specification is crucial for high-speed I/O and bus standards. Typically, jitter specifications are tested by external ATE (automatic test equipment), but the elevating data rate makes it difficult, if possible at all, for the ATE to catch up with the performance requirement. Most of the recent works concentrate on jitter measurement methods. In this work, we propose an on-chip jitter injection technique for receiver jitter tolerance testing. With the target clock rate of 1GHz, this technique can inject 240 ps peak-to-peak jitter with 8 ps resolution誌謝 I 中文摘要 II ABSTRACT III TABLE OF CONTENTS IV LIST OF TABLE VI LIST OF FIGURES VI CHAPTER 1 INTRODUCTION 1 1.1 BACKGROUND AND MOTIVATION 1 1.2 TYPICAL ARCHITECTURE OF THE TRANSCEIVER 2 1.3 JITTER DEFINITION 3 1.4 CATEGORIZATION OF JITTER [7] 4 CHAPTER 2 BASIC CONCEPT OF JITTER TOLERANCE TESTING AND PREVIOUS WORKS 6 2.1 INTRODUCTION 6 2.2 CONCEPT AND OPERATION OF CLOCK AND DATA RECOVERY CIRCUIT 6 2.3 TIMING JITTER AND BIT ERROR 7 2.4 RECEIVER JITTER TOLERANCE MASK 8 2.4.1 Jitter Tolerance Mask as the Specification 8 2.4.2 PJ Mask for Jitter Tracking Ability of CDR 9 2.4.3 Previous Work of Jitter Injection Techniques 12 2.5 REFERENCE WORKS OF PROPOSED TECHNIQUE 14 2.5.1 Current Starved Delay Circuit [16] 15 2.5.2 Shunt Capacitor Delay Circuit [15] 16 2.5.3 Artificial Jitter Injection Technique 17 CHAPTER 3 THE PROPOSED TECHNIQUE AND METHODOLOGY 20 3.1 INTRODUCTION 20 3.2 APPROACH I - ADJUSTED CURRENT STARVED DELAY CIRCUIT 21 3.3 APPROACH II - ADJUSTED ARTIFICIAL JITTER INJECTION CIRCUIT 23 3.4 COMPARISON OF THE TWO APPROACHES 25 3.5 DESIGN METHODOLOGY 25 CHAPTER 4 EXPERIMENTAL RESULT 27 4.1 EXPERIMENTAL RESULT OF PROPOSED TECHNIQUE 27 4.1.1 Experimental Result of the Proposed Technique Methodology 27 4.1.2 Experimental Results for 3 cases of PJ Injection 32 CHAPTER 5 CONCLUSION AND FUTURE WORK 36 REFERENCES 37862027 bytesapplication/pdfen-US抖動容忍度測試內建自我測試jitter injectionjitter tolerance testingBISTthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57712/1/ntu-94-R92943068-1.pdf