呂良鴻臺灣大學：電子工程學研究所李國豪Lee, Guo-HauGuo-HauLee2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57257在無線通訊系統中，為了在有限的頻寬內容納更多的用戶，窄通道間距以及在頻帶間的快速切換是必須滿足的條件。除小數鎖相迴路(fractional-N phase-locked loop)的架構被廣泛的應用來達成這些需求。為了要減輕雜訊及分數突波(fractional spurs)所造成的問題，我們採用了三角積分調變器(delta-sigma modulator)來減小在頻率合成器頻寬內之雜訊。如此可改善分數突波以及雜訊表現。 本論文實現了一個包含單晶壓控震盪器的2.4 GHz ISM頻帶三角積分調變除小數頻率合成器。藉由運用E-TSPC形式的預除器，除法器電路可以同時實現高速除頻及低功率消耗的特點。此除法器並不需要額外消耗大量功率的預放大器(preamplifier)或緩衝級來驅動。整體晶片包含相位頻率偵測器(PFD)，電荷幫浦(CP)，壓控震盪器(VCO)以及多除數除法器(MMD)。低通濾波器的部份由外接元件所實現。三角積分調變器的輸出由向量產生器(pattern generator)所提供。晶片以台積電0.35-μm 2P4M CMOS 製程所製作，頻率合成器的功率消耗為 27 毫瓦。量測於鎖定時的相位雜訊為 -97 dBc/Hz @ 1MHz 偏移。晶片的面積為894 × 855 μm2。In a wireless communication system, narrow channel spacing and fast switching time between channels are desirable to accommodate more users due to the limited frequency band. A fractional-N phase-locked-loop (PLL) architecture is a widely used technique to meet the demands. In order to alleviate the problems caused by fractional spurs and noises, the delta-sigma modulator (DSM) technique is adopted to reduce the phase noise within the synthesizer bandwidth. As a result, the fractional spurs and noises performance can be improved. A 2.4 GHz ISM-band fractional-N frequency synthesizer with a monolithic voltage-controlled oscillator is presented in this thesis. By utilizing the E-TSPC type prescaler, the divider circuit can achieve both high-speed frequency division and low power consumption. No power hunger preamplifier or buffer is needed to drive the divider. The chip is composed of a phase frequency detector (PFD), a charge pump (CP), a voltage-controlled oscillator (VCO) and a multi-modulus divider (MMD). The required low-pass filter is provided by off-chip components in this design. The DSM output is provided by pattern generator. Fabricated in a TSMC 0.35-μm 2P4M CMOS technology, the power consumption of the synthesizer is 27mW. The measured phase noise performance in lock state is -97dBc/Hz @ 1MHz offset. The chip area is 894 × 855 μm2.Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Basic Concepts of PLL 3 2.1 Linear Model of PLL 4 2.2 Basic Building Blocks 7 2.3 PLL Dynamics 16 2.4 Loop Stability 18 2.5 Summary 19 Chapter 3 Fractional-N Synthesizers and Delta-Sigma Modulator 21 3.1 Phase Noise and Spurs 21 3.2 Fractional-N Synthesizers 24 3.3 Delta-Sigma Modulator 26 3.4 Implementation of a 3rd order MASH Delta-Sigma Modulator 30 3.5 Summary 32 Chapter 4 Realization of a CMOS Frequency Synthesizer 33 4.1 Behavioral Simulation 33 4.2 Voltage Controlled Oscillator 34 4.3 Phase Frequency Detector 37 4.4 Charge Pump and Low Pass Filter 39 4.5 Frequency Divider 40 4.6 PLL Implementation 47 4.7 Summary 49 Chapter 5 Experiment Results 51 5.1 Testing Setup 51 5.2 PLL Measurement 53 Chapter 6 Discussions and Conclusions 61 6.1 Discussions of the Measurement Results 61 6.2 Conclusions3292702 bytesapplication/pdfen-US除小數三角積分調變頻率合成器E-TSPCfrequency synthesizerfractional-NDelta-Sigmathesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57257/1/ntu-94-R91943054-1.pdf