AN-YEU(ANDY) WULin, C.-H.C.-H.LinChen, C.-Y.C.-Y.ChenChang, E.-J.E.-J.ChangAN-YEU(ANDY) WU2018-09-102018-09-102011http://www.scopus.com/inward/record.url?eid=2-s2.0-84863068376&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/365386This paper presents a turbo decoder chip design supporting distinct convolutional turbo code schemes in WiMAX and LTE systems. A contention-free vectorizable dual-standard interleaver is proposed to enhance the hardware utilization. Moreover, a warm-up free parallel MAP decoding is proposed to improve the throughput rate. The overall VLSI architecture of the proposed CTC decoder is presented for supporting the WiMAX/LTE systems. This chip fabricated in a core area of 3.38 mm 2 by 90nm CMOS process is measured at 152 MHz with a power consumption of 148.1 mW and a throughput rate of 186.1 Mbps. This chip achieves a high area efficiency of 0.36 bit/mm 2 and a low energy efficiency 0.16 nJ/bit/iteration. © 2011 IEEE.LTE; Multi-standard; Turbo Decoder; WiMAX[SDGs]SDG790nm CMOS; Area efficiency; Chip design; Contention-free; Convolutional turbo codes; Core area; Hardware utilization; Interleavers; LTE; MAP decoding; Multi-standard; Throughput rate; Turbo decoders; VLSI architectures; CMOS integrated circuits; Energy efficiency; Integrated circuits; Standards; Turbo codes; Wimax; Decodingconference paper10.1109/ISICir.2011.6131904