A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems

Dept. of Electr. Eng., National Taiwan Univ.Kuo, J.B.J.B.KuoLou, J.H.J.H.LouSu, K.W.K.W.SuKuoJB2007-04-192018-07-062007-04-192018-07-061995-09http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032036application/pdf206607 bytesapplication/pdfen-USA high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systemsjournal article10.1109/ASIC.1995.580739http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032036/1/00580739.pdf