A Wide Tuning Range Phase Locked Loop for 38 GHz Transceiver in 65 nm CMOS

Khyalia S.KNg Y.-SHUEI WANGZele R.2023-06-092023-06-092021https://www.scopus.com/inward/record.uri?eid=2-s2.0-85118150678&doi=10.1109%2fRFIT52905.2021.9565303&partnerID=40&md5=a7efb9561aa4da90216dab00f6bb9132https://scholars.lib.ntu.edu.tw/handle/123456789/632489This paper presents a 4.75 GHz integer N phase locked loop used in combination with frequency multipliers to achieve local oscillator signal for an 8K drone camera 38-GHz transceiver. This PLL achieves a phase noise of-100 dBc/Hz and-103 dBc/Hz at 100 kHz and 1 MHz offset, respectively. The PLL fabricated in 65 nm CMOS technology occupies a die area of 0.21 mm2. PLL is made programmable to produce accurate LO generation over process, voltage, and temperature variations. © 2021 IEEE.38 GHz; 5G NR.; Integer-N Phase Locked Loop; mmWave; Transceiver; Voltage controlled oscillator[SDGs]SDG7Circuit oscillations; CMOS integrated circuits; Locks (fasteners); Oscillistors; Phase locked loops; Phase noise; Radio transceivers; Variable frequency oscillators; 38 GHz; 5g NR.; 65 nm CMOS technologies; Frequency multiplier; integer-N phase-locked loops; Local oscillators signals; Mm waves; Phase-noise; Voltage-controlled-oscillator; Wide tuning range; 5G mobile communication systemsA Wide Tuning Range Phase Locked Loop for 38 GHz Transceiver in 65 nm CMOSconference paper10.1109/RFIT52905.2021.95653032-s2.0-85118150678