王勝德臺灣大學：電機工程學研究所張郁昌Chang, Yu-ChangYu-ChangChang2007-11-262018-07-062007-11-262018-07-062005http://ntur.lib.ntu.edu.tw//handle/246246/53082Field Programmable Gate Array (FPGA) technologies enabled the implementation of customizable computing platforms using System-on-a-Programmable-Chip (SOPC), where we can configure hardware resources appropriately to match specific application needs. In this paper, a new system design concept and a system design flow are proposed for SOPC paradigm. We describe our design and implementation of an embedded system on an SOPC development board, comparing different design methodologies and implementations using FIR application. Using the proposed design flow, the development cycle can be surprisingly short and the flexibility of SOPC can make us achieve the design specification effectively.1 Introduction 1 1.1 Embedded everywhere . . . . . . . . . . . . . . . . . 1 1.2 System-on-Chip (SOC) . . . . . . . . . . . . . . . . 2 1.3 Field-Programmable Gate Arrays (FPGA) . . . . . . . . 5 1.4 System-on-Programmable-Chip (SOPC) . . . . . . . . . .9 1.5 Contributions and outline . . . . . . . . . . . . . .12 2 Challenges and new design methodology 15 2.1 Comparison of SOC and SOPC . . . . . . . . . . . . . 15 2.2 Challenges of SOC and SOPC . . . . . . . . . . . . . 18 2.3 Proposed design concept . . . . . . . . . . . . . . .23 2.4 Example design flow . . . . . . . . . . . . . . . . .26 3 Implementations of FIR filter 31 3.1 Development platform . . . . . . . . . . . . . . . . 32 3.2 Why use FIR? . . . . . . . . . . . . . . . . . . . . 37 3.3 Finite Impulse Response (FIR) . . . . . . . . . . . .40 3.4 Software implementations . . . . . . . . . . . . . . 43 3.5 Hardware implementations . . . . . . . . . . . . . . 43 4 Results comparison 49 4.1 Software implementations . . . . . . . . . . . . . . 50 4.2 Hardware implementations . . . . . . . . . . . . . . 56 4.3 Performance indexes . . . . . . . . . . . . . . . . .64 4.4 Example scenario . . . . . . . . . . . . . . . . . . 66 5 Discussions 69 5.1 Flexibility and capability of hardware accelerator . 69 5.2 The ease of design decision making . . . . . . . . . 71 5.3 Candidate applications . . . . . . . . . . . . . . . 73 6 Conclusion 79 References 81964878 bytesapplication/pdfen-US設計方法硬體加速可編程邏輯元件可程編系統單晶片有限脈衝響應濾波器Design MethodologyHardware AccelerationFPGASOPCFIRthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53082/1/ntu-94-R91921076-1.pdf