A novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique

Dept. of Electr. Eng., National Taiwan Univ.Wang, Bo-TingBo-TingWangKuo, J.B.J.B.Kuo2007-04-192018-07-062007-04-192018-07-062000-08http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021531application/pdf316991 bytesapplication/pdfen-US[SDGs]SDG7A novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) techniquejournal article10.1109/MWSCAS.2000.952851http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021531/1/00952851.pdf