Dept. of Electr. Eng., National Taiwan Univ.Chang, Hao-ChiehHao-ChiehChangLIANG-GEE CHENHsu, Mei-YunMei-YunHsuChang, Yung-ChiYung-ChiChang2007-04-192018-07-062007-04-192018-07-062000-0502714310http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021468https://www.scopus.com/inward/record.uri?eid=2-s2.0-0033699271&doi=10.1109%2fISCAS.2000.856361&partnerID=40&md5=c9369f2439b0dea3b7481e4328ffbad6This paper presents various analyses of computational behavior, namely the number of datapath operations and memory access, on the core profile level 2 (CPL2) of MPEG-4 Video standard. These analyzed data exploit the load distribution and mode selection of the video system. The exploration of data-flow behavior and its derived computation of MPGE-4 video processing algorithms will then drive through an efficient architecture design.application/pdf470511 bytesapplication/pdfen-USAlgorithms; Computational complexity; Computer architecture; Electric network analysis; Electric network synthesis; Integrated circuit layout; Standards; Video signal processing; Motion picture experts group (MPEG) standards; Video processing algorithms; Digital integrated circuitsconference paper10.1109/ISCAS.2000.8563612-s2.0-0033699271http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021468/1/00856361.pdf