劉深淵臺灣大學:電子工程學研究所王逸新Wang, I-HsinI-HsinWang2010-07-142018-07-102010-07-142018-07-102009U0001-2806200920515400http://ntur.lib.ntu.edu.tw//handle/246246/189126本論文敘述以互補式金屬氧化物半導體電晶體製程設計應用於接收端的自動增益控制放大器以及其後續的類比轉數位訊號轉換器。隨著先進半導體製程的不斷研究進步以及數位訊號處理技術的蓬勃發展，數位電路的功能與效能日益強大，但由於真實世界的訊號都是類比的形式存在並傳遞，在傳遞的過程中，受到各種不同環境的影響與干擾，信號強度與雜訊變化不定，這樣的訊號對數位電路是無法使用的。所以在信號接收端提供穩定的信號大小並將類比訊號轉成數位訊號的電路在各種積體電路上是不可或缺的。先，本論文介紹自動增益放大器的基本原理以及我們實驗測試的兩個自動增益放大器。利用我們提出的方法，可以讓自動增益放大器達到固定的收斂常數，傳輸的速率分別可以達到5Gb/sec與1.25Gb/sec。接著介紹如何將類比信號作取樣以及使用快閃式的架構快速將類比信號轉換為數位信號。在類比信號的取樣上，由於半導體製程上的許多寄生效應會使電路效能降低，我們提出利用差動互補的方式來抵消這些不良的效應，經過實驗，我們的兩個取樣電路分別可以在10GSamples/sec以及13.5GSamples/sec下達到5位元與4位元解析度。在快閃式類比數位轉換器上，我們實際設計驗證利用架構改良與新電路的設計，實現5位元解析度5GSamples/sec以及4位元解析度10GSamples/sec的類比數位轉換器。在先進的深次微米製程之下，電晶體速度加快工作電壓下降。低工作電壓使得類比電路的設計日益困難，所以我們利用先進製程的高速特性，提出時間域的設計方式，將類比電壓轉換成時間長短來作訊號的處理。我們實際實驗完成了8位元20MSamples/sec與解析度可調的積分型類比數位轉換器。最後我們也設計完成時間域的快閃式類比數位轉換器，模擬結果顯示在500MSamples/sec的轉換速率下可達到6位元的解析度。後，在未來的發展上，我們不只能在時間域進行類比數位的轉換；相類似的，在頻率域進行類比數位轉換也是具有發展潛力的。This thesis describes the design of automatic-gain-control amplifiers and the following analog-to-digital data converters using CMOS process technologies. With the progress of semiconductor process and the development of digital signal process technique, the function and the performance of digital circuits become more and more strong. However, real-world signals are analog. When signals are transmitted, signal strengths are different due to different environments and interferences so that they could not be used in digital circuits. Therefore, providing stable signal strength and converting analog signal as digital output data in receivers is indispensable in all kinds of integrated circuits.irst, this thesis introduces basic fundamentals of automatic-gain-control amplifier and two of our experimented automatic-gain-control amplifiers. By our proposed methods, variable-gain amplifiers which have the characteristic of exponential gain amplifiers so that automatic-gain-control amplifiers have constant settling time and their data rates achieve 5Gb/sec and 1.25Gb/sec, respectively. Second, track-and-hold circuits for high-speed analog-to-digital data converter are presented. When sampling an analog signal, many parasitic effects degrade the performance of the circuit. To deal with these problems, two track-and-hold circuits are proposed by using the differential cancellation method to cancel these effects. According to experimental results, the track-and-hold circuits achieve 5-bit 10GSamples/sec and 4-bit 13.5GSamples/sec. respectively. In the flash analog-to-digital data converters, modified architecture and some techniques are adopted to improve performances of bandwidth and circuit.n advance nanoscale CMOS process, transistor has two features of high operation speed and low supply voltage. The low supply voltage makes analog circuits design becomes more and more difficult. The time-domain design methodology which transfers the analog voltage into time-domain signal for data conversion is proposed. An 8-bit 20MSamples/sec integrating analog-to-digital data converter with resolution variable is experimented and discussed. Finally, a time-domain flash analog-to-digital data converter is also designed and implemented in 65-nm CMOS process. According to simulation results, it achieves resolution of 6-bit at 500MSamples/sec.List of Figures Xist of Tables XVIhapter1 Introduction 1.1 Motivation 1.2 Thesis overview 3hapter2 Automatic-Gain-Control Amplifiers 5.1 The basics 5.2 Work 1: A 5Gb/sec CMOS Automatic-Gain-Control Amplifier 8.2.1 Introduction 8.2.2 Circuit Description 9.2.2.1 Architecture 9.2.2.2 Variable Gain Amplifier 10.2.2.3 Peak Detector & Integrator 13.2.3 Experimental Results 13.3 Work 2: A 1.25-Gb/sec CMOS Automatic-Gain-Control Amplifier 17.3.1 Introduction 17.3.2 Architecture 18.3.3 Circuit Description 20.3.3.1 Two cascaded VGAs 20.3.3.2 Remaining Circuits 23.3.4 Experimental Results 26.4 Summary 32hapter3 Track-and-Hold Circuits 33.1 The basics 33.2 Work 1: A 5-bit 10GSamples/sec Track-and-Hold Circuit 34.2.1 Introduction 34.2.2 Circuit Description 35.2.3 Experimental Results 39.3 A 4-Bit 13.5GSamples/sec Track-and-Hold Circuit 41.3.1 Introduction 41.3.2 Circuit Description 42.3.2.1 Clock Feedthrough 42.3.2.2 Signal Bandwidth 45.3.3 Experimental Results 47.4 Summary 51hapter4 Flash Analog-to-Digital Data Converters 52.1 The basics 52.2 Work1: A 5-bit 5GSamples/sec Flash Analog-to-Digital Data Converter 55.2.1 Introduction 55.2.2 Circuit Description 56.2.2.1 Architecture 56.2.2.2 Track-and-Hold Circuit 58.2.2.3 Interpolating Amplifier 61.2.2.4 Comparator 65.2.2.5 Bubble correction circuit and DAC 67.2.3 Experimental Results 67.3 Work 2: A 4-bit 10GSamples/sec Flash Analog-to-Digital Data Converter 71.3.1 Introduction 71.3.2 Merged Interpolation and Reference Voltage 72.3.2.1 Interpolation of Conventional Flash ADC 72.3.2.2 Proposed Architecture 73.3.3 Circuit Implementation 75.3.3.1 Sample-and-Hold Circuit 76.3.3.2 Pre-amplifier and Comparator 76.3.3.3 DAC and Digital Part 78.3.3.4 PLL 80.3.4 Experimental Results 81.4 Summary 84hapter5 Time-Domain Analog-to-Digital Data Converters 86.1 Motivation 86.2 Work 1: An 8-bit 20MSamples/sec ADC 88.2.1 Introduction 88.2.2 Circuit Description 89.2.2.1 Architecture 89.2.2.2 1.5-bit ADC 91.2.2.3 Voltage-to-Pulsewidth Converter 92.2.2.4 Delay-Locked Loop 95.2.2.1 Remaining Circuits 98.2.3 Experimental Results 100.3 Work 2: An Integrating ADC with Variable Resolution 103.3.1 Introduction 103.3.2 Architecture 104.3.3 Circuit Implementation 105.3.3.1 Voltage-to-Pulse Converter 105.3.3.2 Binary Counter 107.3.4 Experimental Results 108.4 Work 3: A 6-bit 500MSamples/sec Time-domain Flash ADC 110.4.1 Introduction 110.4.2 Circuit Description 111.4.2.1 Architecture 111.4.2.2 Voltage-to-Pulsewidth Converter and Non-Overlap Clock Generator 112.4.3 Simulation Results 114.4.4 Chip Layout and Performance Summaries 114.5 Non-Linearity in Time-Domain ADC 115.6 Summary 116hapter6 Conclusion 118.1 Conclusion 118.2 Future work 119IBLIOGRAPHY 121ppendix.. 130ublication List 1335984496 bytesapplication/pdfen-US自動增益控制放大器追蹤保持電路取樣保持電路類比數位轉換器接收機基於零點交越電路延遲鎖項迴路automatic-gain-control amplifiertrack-and-holdsample-and-holdanalog-to-digital data converterreceiverzero-crossing-based circuitdelay locked loopthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189126/1/ntu-98-D91943002-1.pdf