2015-02-012024-05-18https://scholars.lib.ntu.edu.tw/handle/123456789/712929摘要：三維堆疊式積體電路(3DS-IC)在半導體產業中快速發展，使得因應3DS-IC 技術發展之功能性晶圓(Functional wafer)製程技術仍有許多瓶頸急需突破發展。 本計畫將針對功能性晶圓之製程技術分為兩項分項計畫進行，分項計畫一為功 能性晶圓薄化和雷射微鑽孔(Laser viaing)製程研發，由台大研究團隊針對功能 性晶圓所需之導微孔進行製程研究，第一年計畫著重在高品質矽導微孔製作技 術，並將製作出奈米級粗糙度之導微孔孔壁，並導入濕式蝕刻進行雷射變質層 移除。第二年著重在石英及玻璃材料進行導微孔製作研究並調整雷射加工設備 應用至石英及玻璃材料，同樣利用第一年所建構之濕式蝕刻技術移除石英及玻 璃因雷射所產生之變質成層以建立功能性晶專用之雷射製程；分項計畫二為功 能性晶圓穿孔化學機械拋光(Chemical Mechanical Polishing)製程研發，由台科 大研究團隊針對製作導微孔極度銅製程完成之功能性晶圓進行化學機械拋光製 程研究，第一年計畫著重於建立功能性晶圓專用之複合式能量化學機械拋光系 統並針對銅薄膜晶圓及8 吋銅導微孔晶圓之材料移除率及表面粗糙度進行探討， 同時加入玻璃晶圓之化學機械拋光研究。第二年著重於大尺寸複合式化學機械 拋光參數建立，同時加入石英晶圓進行化學機械拋光研究。整合以上兩分項計 畫協助合作廠商建構專用於功能性晶圓之製程發展，以利產學界分享及並提升 台灣功能性晶圓產業競爭力。<br> Abstract: As rapid development of 3D stacking IC (3DS-IC) in semi-conductor industry, the manufacturing technology of functional wafer for 3DS-IC needs to be developed for such demands. This two-year study focuses on developing manufacturing processes of functional wafer that include two sub-projects leaded by NTU and NTUST teams. The sub-project 1 of NTU team develops the wafer thinning technique and micro laser drilling process of via or hole required for functional wafer. The FY-102 of sub-project 1 emphasizes on the manufacturing process of high quality thin wafer with nano surface roughness, and utilizing wet-etching for removing the transformation layer due to laser via process. For the FY-103 of sub-project 1, the research will focus on the laser drilling technique of via or hole, which is used for the substrate of quartz or glass materials, and also established the dedicated process of wet-etching to remove the transformation layer on the quartz/glass surface due to laser via process. The sub-project 2 of NTUST team mainly focuses on the development of chemical mechanical polishing (CMP) process on through silicon via (TSV) of functional wafer. The FY-102 of sub-project 2 is to establish the hybrid-energy CMP system for functional wafer of silicon and glass wafers. The material removal rate (MRR) and surface roughness of copper blanket wafer and 8” copper TSV wafer can be investigated by developed CMP process. Glass wafer or substrate can be investigated for preliminary CMP process. The FY103 of sub-project 2 is to establish the process parameters of hybrid-energy CMP of 8” copper wafer with smaller via diameter and lower thickness deviation. Moreover, the CMP process of glass and quartz wafers will be studied and developed to meet the demands of collaborated company. Finally, this study is to establish a feasible manufacturing process of functional wafer with via, including silicon, glass, and quartz wafers. Results of this study can share fabrication knowledge of academic and industry in Taiwan and therefore to promote the competence of functional wafer industry.三維堆疊式積體電路功能性晶圓晶圓薄化雷射微鑽孔化學機械拋光3DS-ICFunctional waferWafer thinningLaser viaCMP