Dept. of Electr. Eng., National Taiwan Univ.LIANG-GEE CHENChen, Thou-HoThou-HoChen2007-04-192018-07-062007-04-192018-07-061991-06http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032223https://www.scopus.com/inward/record.uri?eid=2-s2.0-0026262668&partnerID=40&md5=3ecc37c646a28eeacd95f81cf0fb3672ChinaMost data in digital signal processing belong to the complex number system. Some characteristics of complex number computations can be utilized to reduce hardware overhead for concurrent error detection (CED) scheme. This paper presents a novel design of CED technique based on realization of direct complex computation approach. It is a time-redundant method, and the recomputation step is performed through exchanging strategy on both the real part and imaginary part circuits in a complex function. The hardware overhead then can be eliminated and the capability of error detection is still robust as duplicated module technique. Since pipelined processing can be introduced to kill the recomputation cycle, the fast Fourier transform (FFT) processor based on pipelined butterfly module with the proposed CED technique is able to achieve real-time fault diagnosis. This technique can be applied to other complex number computing systems, and is more attractive especially in high-speed and high-reliability system.application/pdf427255 bytesapplication/pdfen-USComputational methods; Computer hardware; Error detection; Fast Fourier transforms; Pipeline processing systems; Program diagnostics; Program processors; Concurrent error detection (CED) scheme; Hardware overhead; Imaginary part circuits; Pipelined butterfly module; Real part circuits; Real time fault diagnosis; Recomputation cycle; Time redundant method; Digital signal processingconference paper10.1109/CICCAS.1991.1844922-s2.0-0026262668http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032223/1/00184492.pdf