陳少傑臺灣大學：電子工程學研究所蔡勝中Tsai, Sheng-ChungSheng-ChungTsai2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57363ABSTRACT In this Thesis, we have presented the design of an all-digital phase-locked loop (ADPLL), which consists of a digitally controlled oscillator (DCO), a phase frequency detector (PFD), a control unit and some auxiliary logic circuits. A 16-bit digitally controlled CMOS oscillator uses a 4-stage ring of a modified differential delay cell. The DCO uses the even-stage skew dual-delay path scheme [11], which enables higher operating frequency. The frequency search and the phase tracking are major blocks in a control unit. We use a high sensitivity phase tracking and frequency search algorithm, which consists two D-type flip flop and some logical circuits. In our proposed ADPLL, we implement the DCO by full custom design style while the other circuits are implemented by cell-based design style. In order to rapidly evaluate the structures and algorithms, we model the DCO in Verilog construct, and verify the ADPLL system by Verilog simulator. The ADPLL is designed in the TSMC 0.18μm 1P6M technology. The supply voltage is 1.8V. The simulation results show that when DCO operates at 2.4GHz, the phase error is smaller than 100ps. The system dead zone is smaller than 30ps, and the lock in time is smaller than 30 reference clock cycles (algorithm). The lock-in range is 2.07GHz to 2.56GHz. The power consumption is 106.1mW at 2.4GHz.TABLE OF CONTENTS ABSTRACT ……..…………………………………………………………… i LIST OF FIGURES …………………………………………………………... v LIST OF TABLES ……..……………………………………………………… ix 1 INTRODUCTION …………………………………………………………. 1 1.1 Background …………..…………………….………………………... 1 1.2 Motivation ............................................................................................ 2 1.3 Thesis Organization …….………………………………………..….. 3 2 CLASSIFICATION OF PLL TYPES …..………………………………… 5 2.1 Linear PLL ….….……………………………………………………. 6 2.2 Digital PLL .………..….……………………………………………… 7 2.3 All digital PLL .……………………………………………………… 9 2.4 Comparison ……..………………………….………………………… 10 3 ANALYSIS OF ADPLL ARCHITECTURE ……………………………… 13 3.1 Architecture Introduction ……..……………………………………… 13 3.2 Digitally Controlled Oscillator ……..………………………………… 14 3.3 Mode of Operation in an ADPLL ………..…………………………… 16 3.3.1 Frequency Acquisition …….…..……………………………… 16 3.3.2 Phase Acquisition ….....………………………..……………... 20 3.3.3 Phase and Frequency Maintenance ……..……..……………. 24 4 CRITICAL MODULES IN AN ADPLL ARCHTECTURE …….……… 25 4.1 Phase and Frequency Detector ………………………..……………… 25 4.2 Digitally Controlled Oscillator ……………………………………..… 29 4.3 Summary …….……………………..………………………….……… 32 5 DESIGN AND IMPLEMENTATION ………………………………..…… 33 5.1 Introduction to System Architecture ……..………………………… 33 5.2 Digital of High Sensitivity Phase and Frequency Detector ………..… 34 5.3 Design a Higher Operation Frequency of DCO …..………………… 36 5.4 Control Unit ………………………………………………………..… 41 5.4.1 Frequency Search ………………..…………………………… 41 5.4.2 Phase Tracking ………………….………………………..… 44 5.4.3 Signal Control Unit ….……………..……………..………… 45 5.5 Simulation and Implementation Result ……......……………………. 46 6 CONCLUSION ……………………………………..……………………… 51 REFERENCE ……………………………………………..……………………. 53681872 bytesapplication/pdfen-US全數位式鎖相迴路ADPLLDCOthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57363/1/ntu-94-P92943005-1.pdf