Chien, Y.-R.Y.-R.ChienTsao, H.-W.H.-W.TsaoMao, W.-L.W.-L.MaoHEN-WAI TSAO2018-09-102018-09-102009http://www.scopus.com/inward/record.url?eid=2-s2.0-67650082336&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/347550[SDGs]SDG16Adaptive two-stage equalisation and FEXT cancellation architecture for 10GBASE-T systemjournal article10.1049/iet-com.2008.0150