指導教授：陳少傑臺灣大學：電子工程學研究所王瀚漳Wang, Han-ZhangHan-ZhangWang2014-11-302018-07-102014-11-302018-07-102014http://ntur.lib.ntu.edu.tw//handle/246246/263916本文提出一個新的處理器架構，可以將設計流程所預留的時脈邊值(Timing Margin)完整使用，以達到更省電的效果。在製程極度微縮的時代中，製程所造成的變異越來越難應付。所有的製程都為了提升良率而使用較大的時脈邊值，而這樣的做法會導致晶片過度設計。也因此，有人提出了名為Razor的數位電路，以電路方式偵測晶片上的時脈錯誤(Timing Error)，並且修復這些時脈錯誤以增加整個晶片可使用的時脈邊值。然而，此電路卻會發生突波形狀(spike-shaped)的時脈錯誤，在電壓過低時就會發生無法偵測的問題。因此，我們將此會發生問題的處理器視為一隨機處理器。為了解決前述問題，我們設計了一個新的電路稱為Surger來預測時脈錯誤，並且建立一個程序計數排序(Program Counter Scheduling)機制來使處理器從錯誤中修復。 在這個設計中，我們能使處理器更能不受製程、電壓，與溫度變異的影響。另一方面，我們所建立的Surger是一個可以由軟體來定義此處理器的可靠度。對一個需要高可靠度的設計，如工業電腦，我們可以使用較為嚴峻的樣式來達成；反之，對一個可靠度要求較低的設計，我們亦可使用較為寬鬆的樣式，並使其工作在較低的供應電壓以達成更低功耗與效能維持的目的。藉由這樣的方式，我們將可靠度納入考量，可以達到更彈性的設計，並且使其優於僅考量最糟情況的設計。In this Thesis, we present a new central processor unit (CPU) architecture, which is able to use the whole timing margin and work in a more power efficient way. In advanced process, the process variation is too large to handle. Thus, manufacturers make the slack-time margin larger to ensure the yield rate. On the other hand, Razor cell has been proposed to detect timing error, and recover from it. Considering testability, we need to know the tolerant range voltage as a design factor. However, its error signal detected by Razor is spike-shaped, and could not detect error out of the tolerant voltage range. Thus, we consider the processor with unpredictable behavior as a stochastic processor. For reasons mentioned above, we propose a circuit, Surger, to predict the timing which will cause error, and build a program counter scheduling (PCS) mechanism to recover the core from errors. In this design, we make the processor more independent with process, voltage, and temperature variations. On the other hand, reliability can be software defined in our Surger architecture. For a design that requires high reliability, we can define a pattern to reach this goal. Similarly, for a design that requires low reliability, we can define a pattern to make it working at a lower supply voltage. By this way, we trade off the reliability of a design with its power consumption, and make the design a better-than-worst-case design.ABSTRACT……………………………………………………………………………i LIST OF FIGURES.…………………………………………………………………...v LIST OF TABLES…………………………………………………………………….ix CHAPTER 1 INTRODUCTION 1 1.1 Performance Indices 1 1.2 Pipeline and Parallel Processing 1 1.2.1 Pipeline Architecture 2 1.2.2 Parallel Architecture 5 1.3 Low-Power Design 6 1.4 Stochastic Processor 7 1.5 Motivation 16 1.6 Contributions of this Thesis 17 1.7 Thesis Organization 18 CHAPTER 2 ARM1136 CORE 19 2.1 Architecture 19 2.2 Register Bank 20 2.3 Addressing Modes 23 2.3.1 Addressing Modes for Code 23 2.3.2 Addressing Modes for Data 23 2.4 ARMv6 Instruction Set 24 2.5 Exception 34 CHAPTER 3 DESIGN OF A STOCHASTIC ARM1136 CORE 39 3.1 Architecture 39 3.1.1 Load Store Unit Operation Code 40 3.1.2 Execution Pipeline Operation Code 42 3.2 Control Block 54 3.2.1 Interlock 55 3.2.2 Forwarding 60 3.2.3 Program Counter Scheduling 64 CHAPTER 4 IMPLEMENTATION AND RESULTS 67 4.1 ARM1136 67 4.1.1 Instruction Set 67 4.1.2 Cycle Timing 68 4.1.3 Simulation 71 4.1.4 Performance Analysis 75 4.2 Surger 76 4.2.1 Surger Architecture 77 4.2.2 Delay Cell 79 4.2.3 Results 81 4.3 PCS 87 4.4 Coprocessor 13 88 4.5 Testing plan 89 4.6 Discussion 90 CHAPTER 5 CONCLUSTION 91 REFERENCE………………………………………………………………………...935251582 bytesapplication/pdf論文使用權限：不同意授權隨機處理器錯誤回復錯誤偵測thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/263916/1/ntu-103-R01943120-1.pdf