劉深淵臺灣大學：電子工程學研究所梁鵑伉Liang, Chuan-KangChuan-KangLiang2007-11-272018-07-102007-11-272018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/57316為了減少時脈偏移及雜訊對時脈的影響，延遲鎖定迴路(Delay-Locked Loop)已廣泛的使用於各種時脈相關電路。與鎖相迴路(phase-Locked Loop)相比，其優點為快速鎖定、無穩定性問題、累積的雜訊較少。然而傳統的延遲鎖定迴路亦有其缺點，諸如可鎖定範圍狹窄、諧波項鎖定(harmonic locking)、無法合成頻率、延遲單元不匹配、參考時脈的雜訊無法被衰減……等等。 本論文除介紹延遲鎖定迴路的基本觀念，包含s域(s-domain)和z域(z-domain)的迴路分析，以及類比延遲鎖定迴路和數位延遲鎖定迴路在實踐上的方法外，並提出以延遲鎖定迴路為基礎的全數位、快速鎖定時脈產生器及頻率合成器，解決傳統上延遲鎖定迴路的問題，且得到良好成果。其中時脈產生器以0.18-um CMOS 1P6M technology 實踐，核心面積只需0.06平方公釐，在1.8伏特的電源供應下消耗功率為15毫瓦，並可在二十個週期內完成鎖定，其操作範圍可由1~520MHz，為目前所知面積最小而範圍最大的延遲鎖定迴路時脈產生器；至於頻率合成器則以0.35um TSMC CMOS technology 製作，核心面積為0.216平方公釐. 其除數可調範圍為2~15。輸入範圍由4~200MHz輸出範圍由60~450MHz，為目前所知第一個全數位延遲鎖定迴路的頻率合成器。To minimize timing skews and jitters of the clock signals, Delay-locked loops (DLLs) have been widely used. The DLLs benefit from the unconditional stability, fast locking process and better jitter performance compared with the PLLs. However, various intrinsic problems exist in a conventional DLL such as the narrow operation frequency range, harmonic locking issue, lack of frequency synthesis function, mismatch among delay stages, unsuppressed reference clock noise and so on. Besides introducing the basic concepts of the DLL, the block design issues in the analog DLLs and the control algorithm in the digital DLLs are also discussed. An all-digital ultra wide-range DLL-based clock generator with small area and an all-digital fast-locked programmable DLL-based frequency synthesizer are presented. The former is fabricated in a 0.18-um CMOS 1P6M technology and located with the area of 0.06mm2. Its operation range is from 1MHz to 520MHz. This is the widest range DLL with the smallest area known in the world. The latter is fabricated in 0.35um CMOS technology and occupies the active area of 0.216mm2. The clock multiplication ratio is programmed from 2 to 15. The frequency range of the input and output clocks are 4~200MHz and 60~450MHz, respectively. This is the first all-digital DLL-based frequency synthesizer in the world.Design and Implementation of All-Digital Fast-Locked DLL-Based Clock Generators Contents Abstract III Contents VII List of Figures IX List of Tables XIII 1 Introduction 01 1.1 Motivation 01 1.2 Thesis Overview 02 2 Concepts of Delay Locked Loop 03 2.1 Basic Concepts of Delay-Locked Loop 03 2.2 Analysis of Delay-Locked Loop 04 2.2.1 Type I Delay-Locked Loop 05 2.2.2 Type II Delay-Locked Loop 08 2.3 Design of Analog Delay-Locked Loop 15 2.3.1 Voltage-controlled Delay Line 15 2.3.2 Phase Detector 17 2.3.3 Charge Pump 19 2.4 Design of Digital Delay-Locked Loop 20 2.4.1 Register-controlled DLL 21 2.4.2 Counter-controlled DLL 22 2.4.3 Successive Approximation Register-controlled DLL 23 3 An All-Digital Fast-Locked Ultra Wide-Range Delay Locked Loop 25 3.1 Introduction of Wide Range DLL 25 3.2 System Architecture 29 3.3 Circuit Description 34 3.3.1 Coarse Timing Circuit 34 3.3.2 Pulse Generator 36 3.3.3 Cyclic Delay Line 39 3.3.4 MSAR Controller 43 3.3.5 Duty Cycle Corrector 45 3.4 Simulation Results 48 3.5 Experimental Results 51 3.6 Conclusion 56 4 An All-Digital Fast-Locked Multiplying Delay-Locked Loop 59 4.1 Introduction of DLL Based Clock Multiplier 59 4.2 Circuit Description 63 4.2.1 The Modified SAR Circuits 65 4.2.2 Timing Control Circuits 67 4.2.3 The Digital Phase and Frequency Detector 68 4.2.4 Digital-controlled Delay Line 70 4.3 Performance Analysis 70 4.4 Simulation Results 75 4.5 Experimental Results 77 4.6 Conclusion 83 4.7 Extension 83 5 Conclusion 85 Bibliography 883870438 bytesapplication/pdfen-US延遲鎖定迴路快速鎖定DLLfast-lockedthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57316/1/ntu-95-R93943035-1.pdf