李泰成Lee, Tai-Cheng臺灣大學:電子工程學研究所黃昱融Huang, Yu-JungYu-JungHuang2010-07-142018-07-102010-07-142018-07-102009U0001-1808200914475800http://ntur.lib.ntu.edu.tw//handle/246246/189273本篇論文描述一個具有內插技術之高速六位元六億次取樣互補金氧半快閃式類比數位轉換器。內插技術可以有效的降低輸入負載與前置放大器的數目。這個轉換器主要是針對一些高速的應用，像是超寬頻無線通訊網路，進行最佳化設計。這個類比數位轉換器包含了一個差動式的取樣電路、三級的前置放大器、比較器陣列、以及數位編碼器。在這電路中為了消除電晶體本身的隨機偏壓誤差，在每一級前置放大器的輸出，選用了電阻性平均技巧來減少誤差值。設計的類比數位轉換器實現於0.13μm 1P8M 互補金氧半導體製成，面積為1.115x0.633mm2。量測結果證實此類比數位轉換器在輸入信號為300MHz，操作頻率為600MHz，具有大於30分貝的訊號對雜訊與失真比。整個電路在操作時消耗功率為30mW，並且此電路所用的供應電壓為1.2伏特。This thesis describes a high-speed 6-bit 600MS/s CMOS flash ADC with interpolation. Interpolation technique can reduce the input loading and the number of preamplifier efficiently. This ADC is optimized to operate in high speed application such as ultra-wideband wireless communication network. The analog-to-digital converter consists of a differential track-and-hold circuit, three-stage preamplifiers, comparator array and digital encoder. In order to reduce the transistor random offset error, the outputs of each preamplifier stage are using resistance averaging technique.he designed ADC is fabricated in 0.13μm 1P8M CMOS technology and occupied an area of 1.115x0.633mm2. Measurement result demonstrates that the ADC can achieve a Nyquist rate at 600MS/s with a SNDR above 30dB. The ADC consumes 30 mW from 1.2V power supply.Table of Contents Iist of Figures Vist of Tables XIhapter 1 Introduction 1.1 Motivation 1.2 Thesis Overview 3hapter 2 Overview of High-Speed A/D Converterrchitectures 5.1 Basic Concepts 5.1.1 Signal-to-Noise Ratio 6.1.2 Signal-to-Noise + Distortion Ratio 7.1.3 Resolution and Effective Number of Bits 8.1.4 Nonlinearity 8.2 Flash Architecture 11.3 Folding Architecture 13.4 Two-Step Architecture 15.5 Pipelined Architecture 16.6 Interleaved Architecture 18hapter 3 Design Consideration for Flash A/D Converter 19.1 Building Blocks of Flash ADC 19.1.1 Cancellation of MOS Charge Injection 20.1.2 Comparator 21.2 Averaging Technique 27 3.3 Averaging Termination 30 3.4 Interpolation Technique 31.5 Application (OTFT) 33.5.1 Characteristics 33.5.2 Architecture 34.5.3 Blocks 34.5.4 Simulation Results 36hapter 4 Implementation 37.1 Architecture 37.2 Circuit Building Blocks 41.2.1 Track-and-Hold Amplifier 41.2.2 Reference Buffer 43.2.3 Pre-amplifiers 44.2.4 Dynamic Comparator 47.2.5 Digital Encoder 48.2.6 Gray to Binary & Decimation 49.3 The simulation Results of the Flash ADC 50.4 Layout 52hapter 5 Test and Experimental Results 55.1 Test Setup 55.2 Print Circuit Board Design 56.3 Experimental Results 59.4 Summary 64hapter 6 Conclusions 65.1 Conclusions 65.2 Conclusions 66ibliography 694773831 bytesapplication/pdfen-US快閃式類比數位轉換器電阻平均flash ADCresistance averagingthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189273/1/ntu-98-R96943140-1.pdf