Dept. of Electr. Eng., National Taiwan Univ.Huang, Li-RenLi-RenHuangKuo, Sy-YenSy-YenKuoChen, Ing-YiIng-YiChen2007-04-192018-07-062007-04-192018-07-061995-03http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032111https://www.scopus.com/inward/record.uri?eid=2-s2.0-33845428829&doi=10.1109%2fedtc.1995.470390&partnerID=40&md5=814a3b175b391313a02d4b819f3322f0A new algorithm for the reseeding of multiple polynomial LFSR for pseudorandom teat pattern genera- Tion(PRPG) is proposed in this paper∗. It is based on the Gauss- elimination procedure and the. deterministic test set generated by an ATPG software system for combinational circuits. In addition to the general LFSR model, wc also provide two further improve-ments, mslp and lsmp, to minimize the hardware overhead. Experimental results were obtained on IS- CAS.85 benchmark circuits to demonstrate the effectiveness of this methodology. Complete fault coverage is achieved in all circuits. Low hardware overhead is also maintained with a reasonable test length.application/pdf458577 bytesapplication/pdfen-USTiming circuits; Benchmark circuit; Fault coverages; Gauss elimination; Hardware overheads; Pseudo random; Software systems; Test lengths; Test sets; Software testingconference paper10.1109/EDTC.1995.4703902-s2.0-33845428829http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032111/1/00470390.pdf