Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique

C. H. LinJ. B. KuoJAMES-B KUO2018-09-102018-09-102009-09http://scholars.lib.ntu.edu.tw/handle/123456789/351956Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Techniqueconference paper