Dept. of Electr. Eng., National Taiwan Univ.C.-Y. KuoJIUN-LANG HUANG2018-09-102018-09-102006-04https://www.scopus.com/inward/record.uri?eid=2-s2.0-33751104775&doi=10.1109%2fVTS.2006.10&partnerID=40&md5=bb7b172b6d2de067ff6d6d873b628d3aIn this paper, an on-chip sinusoidal jitter extraction technique based on period tracking is presented. The proposed technique is a viable on-chip solution. It utilizes a variable delay line and a phase comparator to track the signal's cycle lengths without external reference. Digital signal processing techniques are then applied to the obtained signal period sequence to derive the amplitudes and frequencies of the sinusoidal jitter components. Numerical simulations are performed to validate the idea. The results show that the proposed approach can achieve high amplitude and frequency estimation accuracy and is robust in the presence of random jitter components and delay line variations. © 2006 IEEE.application/pdf463308 bytesapplication/pdfBuilt-in self-diagnosis; Built-in self-test; Jitter decomposition; Sinusoidal jitterBuilt-in self test; Computer simulation; Digital signal processing; Electric delay lines; Jitter; Built-in self-diagnosis; Jitter decomposition; Sinusoidal jitter; Chip scale packagesconference paper10.1109/VTS.2006.102-s2.0-33751104775