Tsung-Hsien LinChao-Ching ChiWei-Hao ChiuYu-Hsiang HuangLin, Tsung-HsienTsung-HsienLin2018-09-102018-09-102011-04http://scholars.lib.ntu.edu.tw/handle/123456789/366789[SDGs]SDG7A Synchronous 50% Duty-Cycle Clock Generator in 0.35-μm CMOSjournal article 10.1109/TVLSI.2009.20379102-s2.0-79953125418