Dept. of Electr. Eng., National Taiwan Univ.Fang, J.P.J.P.FangSAO-JIE CHEN2018-09-102018-09-102003http://www.scopus.com/inward/record.url?eid=2-s2.0-84945414757&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/303242In this paper, we introduce a tile-based approach to power planning at the stage of floorplanning. For a given floorplan solution, an associated tile graph of power density is generated, and the temperature of the floorplan is evaluated tile by tile. In contrast to the direct evaluation from the power consumption of circuit blocks and neglecting the effect of heat diffusion, we take the effect of heat diffusion in a die into consideration. Also, we simplify the computing of temperature by way of a tile graph, which make the heat estimation and thus the power planning in the floorplanning stage possible. © 2003 IEEE.application/pdf284760 bytesapplication/pdfBismuth; Circuits; Clocks; Energy consumption; Piecewise linear approximation; Power engineering and energy; Power generation; Temperature; Tiles; Very large scale integration[SDGs]SDG7Bismuth; Clocks; Energy utilization; Networks (circuits); Power generation; Temperature; Tile; VLSI circuits; Circuit blocks; Direct evaluations; Floor-planning; Heat diffusions; Piecewise linear approximations; Power densities; Power engineering and energies; Power planning; Piecewise linear techniquesconference paper10.1109/SOC.2003.12414912-s2.0-84945414757