JUN-CHAU CHIEN2023-06-192023-06-192022-01-01978166549611715292517https://scholars.lib.ntu.edu.tw/handle/123456789/632839This paper presents a single-element VNA electronic calibration (E-Cal) technique implemented in CMOS technology. The structure employs a transmission line (t-line) loaded with twenty distributed switches whose impedance states can be independently modulated during S-parameter measurements. An algorithm that leverages the implementation concepts from the one-port offset-shorts and the two-port Line-Reflect-Reflect-Match (LRRM) calibrations and takes advantage of the loading periodicity and the structure layout symmetry is developed. The calibration method is justified using a 65-nm CMOS test chip and the measurement results are compared with on-chip one-tier TRL calibration using both passive and active devices up to 67 GHz.CMOS | electronics calibration | impedance modulation | LRRM | offset shorts | single element | VNAconference paper10.1109/RFIC54546.2022.98630952-s2.0-85137700999https://api.elsevier.com/content/abstract/scopus_id/85137700999