Shao-Ku KaoSHEN-IUAN LIU2018-09-102018-09-102006-1215497747http://scholars.lib.ntu.edu.tw/handle/123456789/325490https://www.scopus.com/inward/record.uri?eid=2-s2.0-33947422477&doi=10.1109%2fTCSII.2006.885396&partnerID=40&md5=2373989cb902a05abf2132cf2e70b9beAn all-digital fast-locked synchronous duty-cycle corrector is presented. It corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The proposed circuit has been fabricated in a 0.18- μ m CMOS technology. The measured duty-cycle error is between 1.5% and —1.4% for the input duty cycle of 40% ~ 60%. The measured peak-to-peak jitter is 12.9 ps at 1 GHz. The measured operation frequency range is from 0.8 GHz to 1.2 GHz. © 2006, IEEE. All rights reserved.All-digital; duty-cycle corrector (DCC); fast-lockedJitter; Networks (circuits); Synchronization; All-digital fast-locked synchronous duty-cycle corrector; Duty-cycle error; CMOS integrated circuitsjournal article10.1109/TCSII.2006.8853962-s2.0-33947422477WOS:000242948500007