Chang S.S.-YKang W.-CTZU-HSUAN CHANG2023-06-092023-06-092022https://www.scopus.com/inward/record.uri?eid=2-s2.0-85130461140&doi=10.1109%2fVLSI-TSA54299.2022.9771036&partnerID=40&md5=73725201180e5787a54cf3e506bccc03https://scholars.lib.ntu.edu.tw/handle/123456789/632302The accurate model to calculate nanoscale metal resistivity in the advanced logic device is developed. In this model, vicinity compensation for the proximity effect is considered together with bulk, grain boundary, and interface scatterings. With this model, the design optimization of Cu reflow and Ru liner thickness are studied in N10 and N5 technology nodes. Our modeling results agree with experimental insights of metal interconnects, guiding the design of future BEOL metal scheme and Power via applications. © 2022 IEEE.Computer circuits; Grain boundaries; Logic devices; Accurate modeling; Advanced-logic device; Bulk grains; Grain boundary scattering; Grain interface; Interface scattering; Metal resistivity; Nanoscale metals; Proximity effects; Scheme design; Metalsconference paper10.1109/VLSI-TSA54299.2022.97710362-s2.0-85130461140