國立臺灣大學電子工程學研究所吳安宇2006-07-262018-07-102006-07-262018-07-102003-07-31http://ntur.lib.ntu.edu.tw//handle/246246/19988隨著2G/2.5G/3G 高速通訊時代來臨，多標準/多模式共存（Multi Standard/Multi Mode）和單一標準多模式（Multi-Mode in Single Standard）的通訊系統己成為一種 趨勢，以便能夠提供各種不同的通訊傳輸服務。目前通訊IC 多以數位訊號處理器為解 決方式，但通常DSP 的執行速度並無法因應高速傳輸之要求。另一方面，傳統上大多數 特定功能積體電路的設計並不能動態改變模組的功能以因應通訊系統規格改變，且計設 相當費時、所費成本高昂。在本計劃中， 我們提出所謂可重組化通訊引擎 （Reconfigurable Communication Engine），這是一種可重組化（Reconfigurable Computing, RC）的硬體架構，可隨著不同通訊系統格規的改變，將硬體動態重組，達 到符合系統規格要求。我們將針對通訊系統中常用的模組，如維特比解碼器（Viterbi Decoder）、里德所羅門的編碼、解碼器（Reed-Solomon Encoder/Decoder）及快速傅立 葉轉換處理器（Fast Fourier Transform, FFT），在演算法上作分析，期能在演算法階 層改進演算的複雜度，並將每個模組分為硬體核心（Hardcore）和軟體核心（Softcore）。 硬體核心為固定的資料路徑，故硬體線路所需的面積、計算所花的時間和功率的消秏皆 為可預期和可控制。軟體核心則依可重組化設計的觀念，經由控制器規劃控制，依照不 同系統規格的改變，動態調整模組中硬體核心，使整個模組符合系統需求，並使整個模 組可具有高速度、低功率、可擴充性和可攜性。With the advent of the 2G/2.5G/3G high-speed telecommunication, the communication system of multi-standard / multi-mode and the multi-mode in single standard has become a trend as to offer a variety of communication services. On the one hand, DSP (Digital Signal Processing) is often the solution to the design of communication ICs at present. The processing speed of most DSP, however, is not fast enough to handle the great deal of transmitted data in high-speed telecommunication systems. On the other hand, the ASIC designs, in general, can not dynamically adjust the function of modules to maintain the required performance. When the specifications of the system change, it will take a lot of costs and time to redesign the IC circuits. In the project, we propose a novel architecture of communication system to achieve the best balance between the design cost and the functions of transceiver. This architecture is called Reconfigurable Communication Engine (RCE), which can dynamically adjust the functions of modules to meet the altered specifications of the system. We plan to adopt the commonly used modules in communication systems, such as Viterbi decoder, Reed Solomon encoder/decoder, and Fast Fourier Transform (FFT) processor. We will make a detail analysis at algorithm level to reduce the complexity. There are two main cores in each module, including Hardcore and Softcore. The Data path is fixed in the hardcore so that the area, processing speed, and power consumption of modules are expectable and controllable. The conception of the reconfigurable computing is introduced in the softcore design. According to the change of system specifications, we can dynamically adjust the hardcore of modules by controller so as to meet the system requirement. The target design has the property of high speed, low power consumption, scalability, and portability.application/pdf711894 bytesapplication/pdfzh-TW國立臺灣大學電子工程學研究所reporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/19988/1/912215E002044.pdf