FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks

Niraj K. JhaCHUN-YI LEE2024-10-292024-10-292014-05https://scholars.lib.ntu.edu.tw/handle/123456789/722562FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networksjournal article10.1109/tvlsi.2013.2260569