1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture

Dept. of Electr. Eng., National Taiwan Univ.Kuo, J.B.J.B.KuoSu, K.W.K.W.SuLou, J.H.J.H.LouKuoJB2007-04-192018-07-062007-04-192018-07-061993-11N/Ahttp://ntur.lib.ntu.edu.tw//handle/246246/2007041910042632application/pdf227781 bytesapplication/pdfen-US1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecturejournal article10.1049/el:19931402http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910042632/1/00247592.pdf