Dept. of Electr. Eng., National Taiwan Univ.Wang, Shih-ChangShih-ChangWangLin, Hung-YauHung-YauLinKuo, Sy-YenSy-YenKuoHuang, YennunYennunHuang2007-04-192018-07-062007-04-192018-07-061999-12http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021593https://www.scopus.com/inward/record.uri?eid=2-s2.0-0010117075&doi=10.1109%2fPRDC.1999.816231&partnerID=40&md5=ffe595daa30f9516c1f2c1e5e20ec90aIn order to avoid deadlocks, prevention-based routing algorithms impose certain routing restrictions which lead to high hardware complexity or low adaptability. If deadlock occurrences are extremely rare, recovery-based routing algorithms become more attractive with respect to hardware complexity and routing adaptability. A simple architecture where each router is provided with an additional special flit buffer was developed to achieving deadlock recovery. Disha-SEQ and Disha-CON are two deadlock recovery schemes based on such an architecture to accomplish sequential recovery and concurrent recovery, respectively. In this paper, we propose a simple recovery scheme for a 2D mesh with the same router architecture, and reduce drawbacks in Disha-SEQ or Disha-CON, such as hardwired tokens, finding the Hamiltonian cycle, Hamiltonian path labeling for each node, and non-minimal path routing. Moreover, the simulation results show that the proposed scheme has a similar performance to Disha-CON and is better than Disha-SEQ. © 1999 IEEE.application/pdf106577 bytesapplication/pdfen-USComputer architecture; Hamiltonians; Hardware; Network architecture; 2d meshes; Deadlock recovery; Hamiltonian cycle; Hamiltonian path; Hardware complexity; Minimal path; Recovery scheme; Router architecture; Recoveryconference paper10.1109/PRDC.1999.8162312-s2.0-0010117075http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021593/1/00816231.pdf