Dept. of Electr. Eng., National Taiwan Univ.Yang, Ching-YuanChing-YuanYangDehng, Guang-KaaiGuang-KaaiDehngSHEN-IUAN LIU2007-04-192018-07-062007-04-192018-07-061997-0900135194http://ntur.lib.ntu.edu.tw//handle/246246/2007041910042557https://www.scopus.com/inward/record.uri?eid=2-s2.0-0031220941&doi=10.1049%2fel%3a19971175&partnerID=40&md5=35cd7157033476df158d862b09b2ef2aA new high-speed divide-by-4/5 counter is developed. Based on this divide-by-4/5 counter, a 3V 2M ∼1.1 GHz dual-modulus divide-by-128/129 prescaler fabricated with 0.6μm CMOS technology is presented. Its maximum operating frequency of 1.11 GHz with power consumption of 19.2mW has been measured at a 3V supply voltage. In addition, for a power supply of 1.5V, the circuit consumed 2.67mW at a maximum input frequency of 520MHz.application/pdf297960 bytesapplication/pdfen-USCMOS integrated circuits; Dividing circuitsCMOS integrated circuits; Counting circuits; Flip flop circuits; Logic gates; NAND circuits; Timing circuits; Waveform analysis; Dual modulus prescaler; Dividing circuits (arithmetic)journal article10.1049/el:19971175http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910042557/1/00629534.pdf